Accelerating Lattice Reduction with FPGAs

Accelerating Lattice Reduction with FPGAs

Source :

• Lecture Notes in Computer Science [ 0302-9743 ] ; 2010.

Descripteurs français

• Wicri :
  • topic : Cryptographie, Logiciel, Prix unitaire.

English descriptors

• KwdEn :
  • Actual number, Algorithm, Bottom layer, Clock cycles, Communication cost, Control unit, Corresponding subtree, Cryptography, Cryptology, Cryptosystems, Detrey, Enumerating vectors, Enumeration, Enumeration algorithm, Enumeration tree, Euclidean lattices, Fpga, Fpga accelerator, Fpga implementation, Fpgas, Gaussian, Gaussian approximation, Gaussian estimate, Gaussian heuristic, Granularity, Granularity level, Heidelberg, Heuristic, Homomorphic encryption, Ideal lattices, Implementation, Input basis, Integer part, Intel core, Lattice, Lattice attacks, Lattice problems, Lattice reduction, Lncs, Local variables, Master machine, Matrix, Memory requirements, Multiplier, Nguyen, Node, Parallel implementation, Parallelization, Parallelization technique, Partial sums, Performance estimations, Pohst enumeration algorithm, Possible values, Proc, Randomized reductions, Real number, Resource usage, Schmidt matrix, Short vectors, Shortest, Shortest lattice vector, Shortest lattice vector problem, Shortest vector, Shortest vector problem, Software, Software implementation, Solver, Space complexities, Speed grade, Sphere decoding, Springer, Squared norm, Stehl, Stoc, Subtree, Subtrees, Total traversal rate, Traversal, Traversal rate, Unit price, Whole enumeration tree.
• Teeft :
  • Actual number, Algorithm, Bottom layer, Clock cycles, Communication cost, Control unit, Corresponding subtree, Cryptography, Cryptology, Cryptosystems, Detrey, Enumerating vectors, Enumeration, Enumeration algorithm, Enumeration tree, Euclidean lattices, Fpga, Fpga accelerator, Fpga implementation, Fpgas, Gaussian, Gaussian approximation, Gaussian estimate, Gaussian heuristic, Granularity, Granularity level, Heidelberg, Heuristic, Homomorphic encryption, Ideal lattices, Implementation, Input basis, Integer part, Intel core, Lattice, Lattice attacks, Lattice problems, Lattice reduction, Lncs, Local variables, Master machine, Matrix, Memory requirements, Multiplier, Nguyen, Node, Parallel implementation, Parallelization, Parallelization technique, Partial sums, Performance estimations, Pohst enumeration algorithm, Possible values, Proc, Randomized reductions, Real number, Resource usage, Schmidt matrix, Short vectors, Shortest, Shortest lattice vector, Shortest lattice vector problem, Shortest vector, Shortest vector problem, Software, Software implementation, Solver, Space complexities, Speed grade, Sphere decoding, Springer, Squared norm, Stehl, Stoc, Subtree, Subtrees, Total traversal rate, Traversal, Traversal rate, Unit price, Whole enumeration tree.

Abstract

• https://api.istex.fr/document/2900FDFB0BEF6C5C276B9C3D2F9414F9305194EF/fulltext/pdf

Affiliations:

• Australie, France
• Grand Est, Lorraine (région)
• Vandœuvre-lès-Nancy

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